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zeiro
Joined: 11 Feb 2009
Posts: 4
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 Posted: 27.03.2009, 14:06 Post subject: TC bei PWM |
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Hi,
Ich habe mir einen DNP/9200 SK23 gekauft und möchte ein PWM realisieren, dazu habe mich dabei an das Dokument http://www.atmel.com/dyn/resources/prod_documents/doc2682.pdf gehalten. Leider bringe ich den Counter (siehe TC_CV) nicht zum laufen.
Ich hoffe dass mit mir jemand dazu einen Tipp geben kann. Danke.
Hier mein c-Code:
| Code: |
//*-------------------------------------------------------------------------------------------------------
//* File Name : pwm.c
//* Object : DIL/NetPC DNP9200 - Timer Counter - Dual PWM generation
//* Author : AT91 Application Group
//*-------------------------------------------------------------------------------------------------------
//* Configure the channel 3 of the Timer Counter(TC) of the AT91RM9200 to aim dual waveform generation :
//* - clock selected = MCK / 128
//* - Register A compare toggle TIOA3 when reached
//* - Register B compare toggle TIOB3 when reached
//* - Register C compare toggle TIOA3 and TIOB3 when reached
//*-------------------------------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <string.h>
#include <sys/mman.h>
#include <signal.h>
/*Timer Counter Header, Timer Counter Offset: 0xFFFA0000, TC Channel3 Offset 0x4000*/
#define TC3_CCR (*(pTIMER_BASE + 0x4000 / 4)) //Channel Control Register
#define TC3_CMR (*(pTIMER_BASE + 0x4004 / 4)) //Channel Mode Register
#define TC3_CV (*(pTIMER_BASE + 0x4010 / 4)) //Counter Value
#define TC3_SR (*(pTIMER_BASE + 0x4020 / 4)) //Status Register
#define TC3_RA (*(pTIMER_BASE + 0x4014 / 4)) //Register A
#define TC3_RB (*(pTIMER_BASE + 0x4018 / 4)) //Register B
#define TC3_RC (*(pTIMER_BASE + 0x401C / 4)) //Register C
#define PIOB_PDR (*(pPIO_BASE + 0x0604 / 4)) //PIO Disable Register
/* TC_CMR: Timer Counter Channel Mode Register Bits Definition*/
#define TC_CLKS_MCK128 0x0003 /*set bit 1 and 2*/
#define TC_CLKS_MCK2 0x0000 /*set bit 0*/
#define TC_EEVT_XC0 0x0400 /*set bit 10*/
#define TC_CPCTRG 0x4000 /*set bit 14*/
#define TC_WAVE 0x8000 /*set bit 15*/
#define TC_ACPA_TOGGLE_OUTPUT 0x00030000 /*set bit 16 and 17*/
#define TC_ACPC_TOGGLE_OUTPUT 0x000C0000 /*set bit 18 and 19*/
#define TC_ASWTRG_SET_OUTPUT 0x00400000 /*set bit 22*/
#define TC_BCPB_TOGGLE_OUTPUT 0x00300000 /*set bit 24 and 15*/
#define TC_BCPC_TOGGLE_OUTPUT 0x0C000000 /*set bit 26 and 27*/
#define TC_BSWTRG_SET_OUTPUT 0x40000000 /*set bit 30*/
/*TC_CCR: Timer Counter Control Register Bits Definition*/
#define TC_CLKEN 0x1 /*set bit 1*/
#define TC_CLKDIS 0x2 /*set bit 2*/
#define TC_SWTRG 0x4 /*set bit 3*/
/*PIO Controller*/
#define PIOTIOA3 6
#define PIOTIOB3 7
volatile unsigned int *pPIO_BASE, *pTIMER_BASE;
void *pMapmemory(off_t phy_addr, size_t phy_lenght)
{
#define MAP_PAGESIZE 4096UL
int iFd;
void *pMem;
if ((phy_addr % MAP_PAGESIZE) != 0) {
fprintf(stderr,"physical address not aligned on PAGESIZE boundary!\n");
return(NULL);
}
if ((phy_lenght % MAP_PAGESIZE) != 0) {
fprintf(stderr,"physical lenght not aligned on PAGESIZE boundary!\n");
return(NULL);
}
/* open mem device for read/write */
iFd = open("/dev/mem", O_RDWR | O_SYNC);
if (iFd < 0) {
fprintf(stderr,"open of /dev/mem fail !\n");
return(NULL);
}
/* get pointer to DNP9200 memory */
pMem = mmap(NULL,
phy_lenght,
(PROT_READ | PROT_WRITE),
MAP_SHARED,
iFd,
phy_addr);
if ((pMem == MAP_FAILED) || (pMem == NULL)) {
fprintf(stderr,"mmap of /dev/mem fail !\n");
return(NULL);
}
/* close mem device */
if (close(iFd) != 0)
fprintf(stderr,"close of /dev/mem fail !\n");
return(pMem);
}
int init_mem(void)
{
// check user identity
if (geteuid() != 0) {
fprintf(stderr, "No root access rights !\n");
exit(1);
}
/* map AT91 PIO register space at 0xFFFFFF000 / size 4096 bytes */
pPIO_BASE = pMapmemory(0xFFFFF000, 0x00001000);
if (!pPIO_BASE) {
fprintf(stderr,"MMAP PIO_BASE fail !\n");
exit(1);
}
/* map AT91 PIO register space at 0xFFFFFF000 / size 65536 bytes */
pTIMER_BASE = pMapmemory(0xFFFA0000, 0x00010000);
if (!pPIO_BASE) {
fprintf(stderr,"MMAP TIMER_BASE fail !\n");
exit(1);
}
return(0);
}
int main(void)
{
printf("+-----------------------------+\n"
"| DIL/NetPC DNP/9200 PWM-DEMO |\n"
"+-----------------------------+\n");
init_mem();
TC3_CCR = TC_CLKDIS; /*Disable Clock Counter*/
PIOB_PDR = (1 << PIOTIOA3) | (1 << PIOTIOB3);
//Timer/Counter 1 mode configuration
TC3_CMR =
TC_BSWTRG_SET_OUTPUT | /* BSWTRG : software trigger set TIOB */
TC_BCPC_TOGGLE_OUTPUT | /* BCPC : Register C compare toggle TIOB */
TC_BCPB_TOGGLE_OUTPUT | /* BCPB : Register B compare toggle TIOB */
TC_ASWTRG_SET_OUTPUT | /* ASWTRG : software trigger set TIOA */
TC_ACPC_TOGGLE_OUTPUT | /* ACPC : Register C compare toggle TIOA */
TC_ACPA_TOGGLE_OUTPUT | /* ACPA : Register A compare toggle TIOA */
TC_WAVE | /* WAVE : Waveform mode */
TC_CPCTRG | /* CPCTRG : Register C compare trigger enable */
TC_EEVT_XC0 | /* EEVT : XC0 as external event (TIOB=output) */
TC_CLKS_MCK128 ; /* TCCLKS : */
//Compare regisers initialization
TC3_RC = 0x80E8; /*1kHz PWM generation*/
TC3_RB = 0x4074; /*30% duty cycle on TIOB3*/
TC3_RA = 0x26AC; /*50% duty cycle on TIOA3*/
TC3_CCR = TC_CLKEN; /*Enable the clock coounter*/
TC3_CCR = TC_SWTRG; /*Trig the timer*/
for(;;)
{
printf("TC3_SR %X\n",TC3_SR);
printf("TC3_CV %X\n",TC3_CV);
printf("TC3_CMR %X\n",TC3_CMR);
}
return(0);
} |
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Ole
Joined: 26 Nov 2008
Posts: 20
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| Posted: 25.08.2009, 15:58 Post subject: |
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Mir fallen dazu 2 Dinge ein:
1. Die TIO Pins wirklich als TIO pins konfigurieren
2. Die Clock im Power Management Register oder wie der heisst enablen.
... und evt. auch noch im AIC Register, dann sollte es gehen  |
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